Field Programmable Clock (FPC)
The FPC is a unique solution to the problem of optimizing RHP performance versus clock speed. Before the invention of the FPC, designers using FPGA implementations of RHPs were constrained to single, fixed clock speeds. This often meant days of hand tweaking the design to meet timing spec. In addition, the slightest change in the design would often require re-tweaking. It also meant that users could not take advantage of very fast designs since they required a clock faster than the available clock.
The FPC allows users to select the clock frequency that is optimal for their design. The FPC consists of a programmable PLL clock generator and a 10 MHz timebase. The FPC is programmed by the FPGA so users can simply compile their design, perform a default timing analysis to derive the maximum clock speed for their design, dial this number into the FPC programming module and recompile their design. When the design is uploaded into the FPGA, the FPC is automatically set to the desired clock frequency.
Pictured above is the FPC at roughly 2x real size. Its actual size is the same footprint as a 14-pin DIP (pins 1, 7, 8, and 14 are identitical to those found on the standard 14-pin crystal oscillator). The FPC features
The FPC is available only in assembled form for $34.99 + S&H.
Currently, purchases can be made only by check or money order. Please contact email@example.com for further information. Allow 2-4 weeks for delivery.
Software to calculate PLL parameters for the FPC can be found at http://www.cypress.com/pub/software/bc_3e.exe (self-extracting .exe for PC with all flavors of windoze; .exe archive includes a readme file)
FPC datasheet in HTML format.
Last modified by firstname.lastname@example.org Thu Nov 20 05:42:55 1997
This page has been accessed at least times since the counter was last reset, or November 20, 1997 whichever is more recent.